Researching neural network efficiency at the intersection of machine learning and hardware design.
Graduated MS/BS student at Worcester Polytechnic Institute working on making neural networks faster, more efficient, and deployable on edge devices. My research spans model compression, neuromorphic computing, and hardware acceleration.
Novel quantization technique for fully binary weight neural networks (including first and last layers) outperforming STE, especially at depth, achieving a +10%, +13%, and +22% improvement over STE on binary ResNet50 architectures for ImageNet, CIFAR-100, and CIFAR-10 datasets. Preparing January submission.
Under review
Built attention-based neural network for side-channel attacks on masked AES-128 for the ATMega32 chip (dataset from ASCAD), achieving key recovery in under 20k power traces where classical SNR-based power analysis fails due to hardware countermeasures. This reveals an input-invariant attention behavior (r=0.985 correlation across traces, 5% class variance), revealing attack exploits timing artifacts rather than data-dependent leakage, fundamentally different from traditional (template) methods. Research suggests importance of desync techniques against ML based attacks.
A project that took open source blitz data from lichess.com and created a CLAP/CLIP-like model using InfoNCE loss to seperate different players from each other in a "chess player style embedding" space.
The image below shows a 2D embedding space of many games fitted with a gaussian mixture model to determine a correlation between elo and style.
Write up coming soon.
Designing and implementing a spiking neural network accelerator for semantic segmentation on FPGA. Developed a custom Python-to-RTL pipeline with FPGA-specific quantization-aware training (QAT) and a buffered hardware architecture that exploits sparsity in spiking networks.
Targeting low-energy classification and semantic segmentation for autonomous driving applications using the Cityscapes dataset.
Image shows MNIST digit input to the spiking neural network over timesteps, using rate encoding generated at the RTL level with a pixelwise LFSR pseudo-random number generator.
Developed semantic segmentation dataset (1,400+ days) for detecting coronal holes on the solar surface. Built custom annotation pipeline and trained progressively growing U-Net models, improving IoU by 15%. Joint first author.
A smaller project, focusing on creating a very small systolic array for the small system on chip (SoC), Croc, on an 180 nm process. This project explores making a systolic array for low power with fp4 and and iterated low power individual processing elements.
This project optimized for small low power 4x4 matrix multiplications, utilizing careful loading and memory management with a custom software driver, circular queueing format, and multiplexed output loading system.
Using a generalized modification of A*, can solve and build from existing Bananagrams boards in seconds.
As part of our cirriculum at Worcester Polytechnic Institute, we do an Interactive Qualifify Project (IQP). My IQP was done in Acadia National Park in Maine, working with the National Park and Friends of Acadia. From IQP we wrote an in depth report of our findings and recommendations.
A small animation using the Python package Manim to show how the small signal model works. In the future, I hope to flesh this explanation out to be more comprehensive.
